In modern communication systems, during a process of transmitting information from a source to a destination, the information usually needs to be forwarded by a forwarding device. Up to now, the development of the forwarding technology experiences the following five stages.
The first generation forwarding technology mainly adopts software-based centralized forwarding and bus switching technologies. FIG. 1 is a schematic diagram illustrating a structure of a first generation forwarding device. As shown in FIG. 1, interface cards connect to a Central Process Unit (CPU) through internal buses; wherein, the CPU is responsible for all transaction processes, including route collections, forwarding and device managements, etc. After receiving a packet, interfaces on the interface cards transfer the packet to the CPU through the internal bus, and the CPU transfers the packet to another port after all processing steps. Such forwarding devices can be constituted by a computer with several inserted interface cards.
The second generation forwarding technology mainly adopts a Cache technology. FIG. 2 is a schematic diagram illustrating a structure of a second generation forwarding device. As shown in FIG. 2, a Cache is added to the interface card of the first generation forwarding device, and some commonly used routing information are saved in the interface card using the Cache technology. Since network users usually visit a few sites, most packets can be forwarded directly through a routing table in the Cache of the interface card, so as to reduce the demand for the bus and the CPU. Only when the routing information of the packet can not be found in the Cache, the packet will be sent to the CPU to be forwarded.
The third generation forwarding technology adopts a full distributed architecture, i.e. a technology with independent routing and forwarding functions. The forwarding device includes a main control board and service boards. Wherein, the main control board is used to manage the whole equipment, collect and calculate routes, and distribute the calculated forwarding table to each service board. FIG. 3 is a schematic diagram illustrating a structure of a service board of a third generation forwarding device. As shown in FIG. 3, the service board includes several forwarding CPUs, each CPU independently forwards packets according to the stored routing table. In addition, the rapid development of buses makes it possible to forward packets between service boards through buses without the help of the main control board, which realizes parallel high speed processing, and thereby dramatically improves the processing ability of the forwarding device.
The fourth generation forwarding technology adopts hardware to implement all the details in the forwarding process. FIG. 4A is a schematic diagram illustrating a structure of a fourth generation forwarding device. As shown in FIG. 4A, large-scale Field Programmable Gate Array (FPGA) forwarding engines or more advanced programmable Application Specific Integrated Circuit (ASIC) forwarding engines are adopted to replace the CPUs in each service board of the third generation forwarding device, which solves the problems of a low performance, a low port density and a low velocity of the CPU. In addition, a switching matrix, which adopts a CrossBar technology or a shared memory technology, is adopted to replace the switching bus in the third generation forwarding device. Typically, early Gigabit Switch Routers (GSRs), which have a capacity of Gigabit, are the fourth generation forwarding devices.
FIG. 4B is a schematic diagram illustrating a structure of an FPGA/AISC forwarding engine in the fourth generation forwarding device. As shown in FIG. 4B, a forwarding service flow 41 is integrated in the FPGA/AISC forwarding engine 40. The forwarding service flow generally includes one or more hardware pipelines, wherein, a hardware pipeline may include several Steps, such as Step 1, Step 2 . . . Step n, and each step is implemented by a corresponding programmable device. In addition, the FPGA/AISC forwarding engine 40 also includes a special hardware unit 42, such as, a hardware interface unit used for visiting external memories, a unit used for primary link layer analysis of packets, an interface processing unit connected with a Ternary Content-Addressable Memory (TCAM), or an internal integrated Media Access Control (MAC) unit, etc. Since all the service forwarding flows are implemented by hardware in the fourth generation forwarding technology, its performance is excellent, stable and reliable.
The fifth generation forwarding technology adopts programmable Network Processors (NPs) exclusively designed for IP networks. FIG. 5A is a schematic diagram illustrating a structure of a fifth generation forwarding device. As shown in FIG. 5A, the hardware structure of the fifth generation forwarding device technically inherit that in the fourth generation forwarding device, it also includes the forwarding engine and the switching matrix, but adopts the programmable NPs especially designed for the IP networks as the forwarding engines in the key IP service flows. Typically, Huawei NE 80/40 series products etc. are the fifth generation forwarding devices.
The NP is a programmable device especially used in the communication field, such as, packet processing, protocol analysis, routing search, voice/data aggregation, firewall and Quality of Service (QoS). Currently, the NP generally refers to a network processor of integrated services, i.e. a network processor for implementing diversified forwarding functions.
FIG. 5B is a schematic diagram illustrating a structure of the NP which is adopted as the forwarding engine in the fifth generation forwarding device. As shown in FIG. 5B, the NP 50 usually consists of several Micro Engines (MEs) 51, a hardware co-processor 52, a special hardware unit 53 and an embedded CPU 54. The MEs 51 operate in parallel and implement the forwarding control process in software. The co-processor is used for improving the processing performance of some complicated, standard operations, such as memory operations, searching algorithms of the routing table, QoS congestion control algorithms and traffic scheduling algorithms, etc. It combines the flexibility and the high performance of the service. The special hardware unit 53 is a hardware accelerator, which is optional based on practical situations. For example, the unit can be a unit used for primary analysis of a packet when the packet entering into the NP according to the configured type of the port, or a unit used for generating sequence numbers and guaranteeing the forwarding order, or a unit used for accelerating the visit to external memories, or a hardware used for automatic memory management. The embedded CPU54 acts as an intermediate between the NP and other periphery CPUs, and can also be used for some NP management functions or link layer protocol processing functions, and also some ME software diagnosing and debugging functions of the NP.
The performance of the NP is high. Since several or even dozens of forwarding MEs, hardware co-processors and hardware accelerators are integrated in the NP, many algorithms in the forwarding process can be implemented by hardware, and thereby achieve a higher searching, forwarding performance, and realize “hardware forwarding” on the premise that the ME implements the complicated congestion control, queue scheduling, flow classifying and QoS functions. For example, some NPs, such as NPs supporting 2.5 Gbps forwarding speed, NPs supporting 10 Gbps and NPs supporting 40 Gbps, are currently put into commercial use.
The function expansion of the NP is flexible. Since the ME is programmable, once there are new technologies or demands, it is very convenient to realize them through software programming, it is also convenient to add or remove system functions by adding or removing software modules. Therefore, it is possible to tailor customized development for special user demands, which means, to develop products satisfying different requirements of users through adding or removing modules within a short period of time. While in the case of the FPGA which is adopted to implement the function extension, it is necessary to modify pin functions, debug and update once again. In most cases, it is also necessary to change other special hardware units, which brings about potential trouble to the reliability of the system. If the AISC is adopted to implement the function extension, since the new functions can not be added, the chip must be re-designed and replaced. As to the development period, the software development usually takes 6 months, but the implementation of the FPGA needs 18 months, and the ASIC costs even longer, generally 2˜3 years. Along with the development of C programming language being adopted in the NPs, the software development cycle will become shorter and shorter. Therefore, comparing with the fourth generation forwarding technology, the NP has a more flexible function expansion capacity.
The reliability of the NP is high. Most NP systems are implemented by one or two chips, and all chips have undergone strict tests and diversified anti-interference and devastating experiments by manufactures, which can dramatically improve the reliability of the NP systems. Therefore, the NP is very suitable for developing data communication products of telecommunication level.